Computer systems continue to evolve, with ever faster processing speeds, greater data handling capabilities, and increasing storage capacity. Computers have also been steadily reduced in size. This size reduction is most apparent in the laptop, notebook, tablet, and hand-held computer markets. While desiring to continuously decrease the size and weight of laptops, notebooks, and hand-held computers, manufacturers have also steadily reduced the size and weight of on-board batteries. Because battery-life in laptops, notebooks, and hand-held computers is such an important consideration, power management methods are utilized to increase battery-life.
Conventional computer systems may employ a multitude of power saving features for reducing system power, such as power conservation methods for graphical user interfaces, processors, and memory controllers, which for example, may include frequency reduction, clock-gating, power-gating, low-power DRAM states, low-power I/O modes, and disabling of analog circuits, such as phase-locked loops (PLLs) and delay-locked loops (DLLs). A coordinated engagement and disengagement of these low-power features can enable low-power system states to be utilized for power savings.
However, any level of power-gating and frequency reduction of a system component (e.g., microprocessors and memory controllers) is time constrained based on power mode entry and exit delays. In other words, while deep power savings may be achieved through power-gating and/or frequency reductions, such power-gating and frequency reductions may not be permitted if either the power-gating or the frequency reduction entry and exit times exceed timing constraints. When memory controller states are changed, the memory controller state may be saved, memory controller is powered off and later, memory controller is powered on and its state is restored and this resulting latency must be transparent to any agent requesting memory access. In other words, the deepest power-gating and power saving states may be unreachable because the resulting timing latency is too great.